The invention relates generally to semiconductor logic devices, and more specifically to domino logic circuitry having a novel static output predischarge gate.
Semiconductor operational frequencies are ever increasing, requiring circuitry and processes that support these faster clock rates. Domino circuits have been used in such circuits to speed processing, due to the way in which a domino logic circuit handles data. A typical domino logic circuit receives data on a first transition of a clock, and couples a logically derived signal to external circuitry on a next transition of the clock.
A conventional domino circuit includes dynamic circuitry coupled to static gate circuitry. The dynamic circuitry pre-charges an input of the static circuitry when a clock signal is low, and couples an input data signal to the static circuitry when the clock signal is high. The dynamic circuitry often is n-type metal oxide semiconductor (NMOS) pull-down circuitry, that is operable to pull down the level of a relatively weakly held pre-charged circuit node. The node then provides a stable output to static CMOS circuitry until the next reset phase.
But, the speed of such logic is limited by the time it takes to pre-charge the dynamic circuit node that provides the data signal to the static CMOS circuitry, and by the time it takes to pull down the weakly-held precharged node voltage to provide a low signal level to the static CMOS circuitry. For these reasons and others that will be apparent to those skilled in the art upon reading and understanding this specification, a need exists for a domino logic circuit that reduces the time required to change the state of the static CMOS stage of a domino logic circuit to provide a faster overall signal propagation speed.